Modern test programs for post-silicon testing include a large number of test measurements applied in multiple settings such as different temperatures, supply voltages, and operation modes to meet the demanding quality requirements of the products. In addition to the pass/fail results of each test item, there exist multiple types of correlations in the huge amount of production test data. Identifying and modeling the hidden correlations in the test data could help screen test escapes, which are chips that pass all test items but fail in system-level application.

This thesis focuses on developing revealing features and machine learning algorithms for classifying test escapes based on production test data. In terms of feature engineering, three types of feature sets that represent different aspects of how a chip deviates from the normal population are proposed. In addition, a linear transformation that compacts the critical information for feature reduction and a collection of nonlinear transformations that reveal additional abnormalities of the test escapes are proposed to effectively expose the test escapes as outliers in certain perspectives. We have also developed frameworks exploiting state-of-the-art machine learning algorithms including a support vector machine (SVM), a cascade of AdaBoost classifiers, and an artificial neural network.