The semiconductor industry is confronting an acute problem in the interconnect area--as IC feature sizes continue to be scaled below 22 nm, Cu wires exhibit significant "size effects" resulting in a sharp rise in their resistivity, which in turn has adverse impact both on IC performance and reliability -- in the form of higher communication costs due to increased interconnect delays and chip-level power dissipation, as well as reduced current carrying capacity of the wires. Additionally, designing low-loss and high-quality passive structures becomes increasingly difficult for ultra high-frequency/RF or Terahertz applications. This dissertation explores the feasibility of using carbon nanomaterials such as carbon nanotubes (CNT) and graphene as next-generation interconnects and passive devices to address some of the key performance, energy-efficiency and reliability challenges facing the IC industry--from modeling, design, as well as fabrication perspectives.

On the modeling and design front, this dissertation presents the first and foremost attempt to build a compact circuit model for double/multi-walled CNT interconnects, based on which, the performance of CNT interconnects are analyzed and compared with that of Cu, showing the potential for 50% savings in both delay and power. We are also the first to theoretically illustrate that carbon based interconnects exhibit unique high-frequency behavior in the form of reduced skin effect, which shows great promise for designing low-loss ultra high-frequency interconnects/passive devices and circuits. Moreover, we propose a unique CNT based capacitor design that provides over 4X capacitance density than that required by the International Technology Roadmap for Semiconductors (ITRS) for the year 2014. In addition, we provide the first comprehensive evaluation of CNT vias that are being heavily researched by the semiconductor R&D community, and quantify their impact on the performance and thermal management of the back-end of the chip. En route, we bring forward the key process design requirements for CNT vias.

On the fabrication front, this dissertation presents a novel process that, for the first time, enables fabrication of high-density, long (over 100 microns) and thick (up to microns) horizontally aligned CNT interconnects. The developed process not only yields horizontal CNT interconnects with the lowest reported resistivity, but also enables the first ever fabrication of a CNT based on-chip inductor. Finally, this dissertation includes a first-time study of electrostatic discharge characterization of few-layer graphene (relevant for both active and passive devices), and demonstrates the exceptional robustness of graphene with achieved current density as high as 4.6x108 A/ cm 2.