This thesis work examines the problem of CMOS aging in VLSI integrated circuits. In nanoscale technologies, Negative and Positive Bias Temperature Instability causes an increase over time in the absolute value of the threshold voltage of PMOS and NMOS transistors which results in degraded circuit performance. Current methods to detect and compensate for aging in both digital and combinational logic and memory arrays are presented in this work. My own research contribution in the field of SRAM aging detection is then described. Modifications to standard 6T SRAM cells create a built in sensor which can detect effects of Bias Temperature Instability on the NMOS and PMOS transistors of an SRAM cell. The proposed design allows for a check process, which can observe an increase in transistor threshold voltage as a result of aging effects directly in a cell which is actually used as a memory unit. The proposed modifications allow for detections of aging while having a minimized impact on area and performance of a standard 6T SRAM cell.