Modern semiconductor industry faces skyrocketing design and manufacturing cost as technology advances. Vertical Slit Field Effect Transistor (VeSFET) based ICs have super regular layouts which may significantly reduce manufacturing cost. VeSFETs can be packed densely in an array fashion thus VeSFET-based ICs may achieve smaller footprints than their CMOS counterparts. VeSFET-based ICs also have great energy efficiency, and are good candidate for 3-D integration. In this dissertation, we study VeSFET ICs mapped to various array topologies (canvases), and characterize their area, performance, power, and thermal behaviors. VeSFET-based circuits are implemented by customizing interconnects on pre-manufactured canvases. In this dissertation, we particularly focus on a class of canvases referred to as chain canvases (CCs). CMOS-oriented design automation tools can be easily adapted for CC-based VeSFET designs.

VeSFET ICs based on CCs demonstrate very good performance and low power. Detailed routing for super dense VeSFET layouts can be very challenging because highly congested pins are hard to access. We propose a two-sided routing strategy for VeSFET chips. We show that such routing not only provides much better routability, but also achieves better performance and lower power than one-sided routing. Thermal management constitutes a huge challenge for CMOS or FinFET-based circuits, especially when chips go 3-D. VeSFET provides an alternative thermal-friendly design choice. In this dissertation, we show that temperature increase due to self-heating is very small for VeSFET transistors. At chip level, VeSFET-based 2-D and 3-D chips not only have much lower power density, but also better vertical thermal conductivity than their CMOS counterparts. Finally, we explore VeSFET-based subthreshold circuits for ultra-low power applications.