A power and area efficient approach to embed a continuous time linear equalizer (CTLE) into a clock and data recovery (CDR) circuit for the next generation 100GbE system is presented in this work. The proposed merged CDR/equalizer system is implemented in 65-nm CMOS without extra power penalty, and achieves full-rate operation up to 28-Gb/s. Current-mode-logic (CML) with shunt peaking loads and customized differential pair layout are used to extend the circuit bandwidth. To minimize the area penalty, customized stacked differential inductors have been designed. These inductors achieve an inductance density 3.2 times higher than the standard single-layer design from the PDK library. The CDR/equalizer core occupies 0.33 mm.

2 and draws 104 mA from a 1-V supply. The measured BERof the recovered data is less than 10.

-12 at 27-Gb/s for 2.

11-1 400mVpp inputPRBS data. The measured recovered clock and data rms jitter is 1.0 and 2.6 ps, respectively. The CDR is able to lock to inputs from 26-28-Gb/s with 2.

9-1PRBS pattern. The embedded equalizer enables the CDR to recover a 26-Gb/s 2.

7-1 PRBS data with BER < 10.

-12 after a channel with 9-dB loss at 13-GHz.