Designing robust integrated circuits have become increasingly challenging due to the presence of process variations. One of the main sources of process variations comes from optical lithography, which is the primary technology used for patterning design layouts on wafers. Aggressive scaling of feature size and the postponement of next-generation illumination sources causes serious degradation of on-silicon printed images. As a result, severe pattern distortions may occur, even when various resolution enhancement techniques are applied. In this dissertation, we propose design methodologies to address problems caused by lithography process variability. At the circuit simulation level, we propose a non-rectangular transistor modeling approach that derives an equivalent device gate length and width for accurate postlithography circuit simulations and analyses. Only one equivalent device is built and it is accurate for both on and off modes. At the layout verification level, we propose a hierarchical lithographic hotspot pattern classification system that is both accurate and computationally efficient. We construct our pattern classifiers using support vector machines and use a layout density-based method for pattern characterization. Experimental results show that our method exhibits excellent predictive capability and complements the pattern matching-based methods very well. Last, at the postplacement layout optimization level, we propose an algorithm that detects lithographic hotspots in a given placement of one-dimensional gridded designs and applies local perturbation of cell locations to remove the hotspots. The hotspot detection system is constructed using machine learning techniques. Experimental results show that our method can effectively remove all hotspots while incurring negligible penalty on estimated wire lengths.