Traditional CMOS scaling trends, which allowed designers to exploit the increasing number of transistors at almost constant power consumption, are no longer possible. All the recent trends in CPU designs share one common trend, which is departing from the monolithic design of the processor to a more of integrated chip of many components. These components are cores, accelerators, neural-processing units, imprecise computational units or even communication components. All of these parts need to communicate to accomplish greater computational tasks. They usually do through a network-on-chip. In this dissertation, we examined at three reliability aspects of networks-on-chip in this post traditional-CMOS scaling era. First, we explored using plasmonic modulators to enhance the reliability of the recently proposed nano-photonic signaling used in networks-on-chips.

We characterized the conditions under which hybrid plasmonic/photonic channels would save energy used in tuning the channels. In high assurance systems, of which lack of safety guarantees can be catastrophic or even fatal, non-interference is used to separate critical domains handling critical (or confidential) information from those processing normal (or unclassified) data. We proposed SurfNoC, a provably secure timing-channel free supporting multiple security domains. It is a scheduling technique that guarantees non-interference between domains at a low-latency overhead. We used gate-level information flow tracking to design and verify the security property of the router micro-architecture. The third aspect is deadlock-freedom in hardware circuits on the implementation level. We took an information-flow analysis approach in our investigation due to an insight that all requests and grants of resources are manifested in the signals of the implementation.

We used gate-level information flow tracking techniques, which were previously used to only analyze security properties, to verify conditions necessary and sufficient for deadlock detection. Specifically, we applied GLIFT techniques to cyclic dependency detection and non-preemption verification conditions of the deadlock. This technique constitutes the first step towards proving deadlock freedom on the implementation level by augmenting it with state-space exploration techniques.