When developing a microprocessor, designers are asked to balance a growing number of tradeoffs for a system's intended set of applications. These design decisions, such as sharing cache space between cores, are often statically defined and limit the usability of the processor for other applications. Since processor manufacturers are economically influenced, most resulting designs show a strong affinity towards optimizing common design goals such as high performance and low power usage. Unfortunately, other design aspects can be overlooked or ignored entirely, which is problematic as we enter a new era of computing where processors play an important role in critical systems and security becomes a paramount concern.

To ensure the appropriate security policies are enforced on high assurance systems, designers must often undertake the time-consuming task of redesigning processors from the ground up. This is a cumbersome task and increases in difficulty with an ever-changing threat model with which these systems are concerned. While the resulting systems are successful in mitigating security problems, they pale in comparison to their commercial counterparts in terms of performance. Ideally, the low-cost and high-performance parts being manufactured today for the average user can be leveraged in a system processing data and executing code of mixed trust. In an effort to counter the current state of computing where processors lack security functionality and configurability, new design directions are needed to create processors that can be retrofitted with new hardware in response to different usage models. This dissertation focuses on discovering and analyzing methods of extending an existing design to cater to applications past the one it was originally developed for, with a concentration on security. We show that the functionality of a processor can be extended after making minimal changes to its design. We introduce several novel methods of adding security hardware to processors through the use of 3-D Integration, resulting in processors that are secure without sacrificing performance. We also show how these same methods can be used to make a processor extensible in its computational abilities by augmenting the Instruction Set Architecture (ISA).