Electromigration (EM) is a major reliability problem in modern VLSI, which is caused by material transport due to momentum transfer from moving electrons to atoms. Predominantly, EM occurs in wires with direct currents of large densities such as power and ground (P/G). Signal lines that carry AC or pulsed DC are usually tagged as EM-immune. But, as the wire dimensions continuously scale, EM failures have been also reported in signal lines.

The existing EM design rules are stated as current density limits based on Black's equation, and Blech length effect derived and experimentally justified for metal lines with constant DC only. These rules are helpful in P/G grid design but cannot be used directly for signal lines. A common practice for signal lines with AC and pulsed DC is to impose an upper bound on AVG and RMS current densities. However, simply assigning threshold values for AVG and RMS current densities will usually bring either optimistic or pessimistic conclusions, especially for those cases with short interconnect length and large current densities. More advanced method of treating this problem is to convert the non-steady DC current into its EM equivalent (by setting identical mean time to fail) steady DC current. Some current density-based current conversions have been experimentally verified. However, these methods lack theoretical analyses and are often treated as empirical rules.

We note that atomic flux divergence (AFD), as the fundamental reason causing EM, can be applied to evaluate the EM reliability of signal lines with non-steady DC patterns. We propose a SPICE-based scheme to quantitatively simulate AFD distribution in signal lines, and convert the non-steady DC to its EM reliability equivalent steady DC based on maximum AFD value instead of on current density. The maximum AFD can also be used to predict the EM lifetime and optimize reliability.