As VLSI technologies evolve in More-Moore (smaller feature size via scaling) and More-than-Moore (more functionality via 3-D integration) eras and become increasingly communication centric, interconnects become central to improving the performance and energy-efficiency of VLSI circuits. This dissertation identifies and addresses some of the key technical problems of emerging interconnect structures and materials applicable to both 3-D integrated circuits (3-D ICs) as well as ultra-scaled planar ICs.

In the rapidly growing platform of 3-D ICs, we develop physical models and investigate the extraction of both the parallel admittance (capacitance (C) and conductance (G)) and the series impedance (resistance (R) and inductance (L)) of conventional and new interconnect structures, under a wide range of frequencies (few MHz to 100GHz). We derive both 2D (per-unit-length) analytical CG model and 3D CG extraction methodologies (showing 103 times speed-up against HFSS at similar accuracy level) of Through-Silicon Vias (TSVs), with consideration of MOS effect and ac conduction in silicon. We also obtain a compact capacitance model of Through-Oxide Vias (TOVs) in SOI based 3-D ICs. We then extend our work to investigate the CG/capacitive coupling from TSVs/TOVs to the active regions and provide design guidelines to alleviate noise in active devices. We obtain a fast 2D and 3D RL extraction method for the horizontal interconnects sandwiched between conductive substrates (our 3D RL extraction method shows 18-25X speed-up against HFSS at similar accuracy level), as well as 2D and 3D analytical RL model (<7% error against HFSS) for TSVs, with consideration of skin effect and substrate eddy current effect. All the models and extraction methods are verified against rigorous electromagnetic field solvers.

In the domain of emerging interconnect materials, electrical properties of carbon nanotubes (CNTs) and graphene nanoribbons (GNRs) are investigated. Using Landauer's theory, a conductance model of multi-layer GNRs is derived for predictive analyses. We also extend our TSV RL model for the case of CNT bundles, in which we demonstrate a reduced skin effect. Subsequently, we study the circuit electrical performance of TSVs and horizontal interconnects with different interconnect materials (including Cu, W, CNT and GNR). From these comparative analyses, we illustrate the conditions necessary for making CNTs and GNRs viable alternatives to Cu or W (closely packed SWCNT bundle and multi-layer intercalation doped zz-GNR with smooth edges).

Besides the electrical performance, we also study the thermal performance of interconnects using the thermal-electro analogies. We develop an efficient large scale thermal extraction tool based on an existing electrical resistance extraction tool. We also develop an empirical interconnect thermal model and anisotropic equivalent medium approach based on an existing interconnect capacitance model. We then apply the anisotropic equivalent medium approach in 3-D IC heat dissipation analysis, and demonstrate potential benefits of CNT bundle based TSVs in terms of heat dissipation.